1. Field of the Invention
This invention relates generally to programmable logic devices, and in particular to a system for re-configuring the configurable logic blocks and the programmable routing matrices of a field programmable gate array.
2. Description of the Related Art
The use of programmable logic devices such as field programmable gate arrays ("FPGAs") has become widespread because of the flexibility provided by their re-programmability. An FPGA typically includes an array of configurable logic blocks ("CLBs") that can be programmably interconnected to each other to provide the logic function desired by the user. The Xilinx 1993 data book entitled "The Programmable Logic Data Book," available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, describes several FPGA products made by Xilinx, Inc., assignee of the present invention. This data book is incorporated herein by reference. An FPGA typically includes a regular array of identical CLBs. Each of the CLBs may be individually programmed to perform any one of a number of different logic functions. The FPGA has configurable routing matrices for coupling the CLBs together according to a desired configuration. The FPGA also includes a number of configuration memory cells. The configuration memory cells are coupled to the CLBs for specifying the function performed by each CLB, and to the configurable routing matrices for specifying the coupling of the inputs and outputs of the CLBs. The FPGA also typically includes data storage memory cells accessible to a user during operation of the FPGA, but the discussion here of memory cells refers to configuration memory cells. Each CLB is coupled to several memory cells that specify the function that the CLB will perform, and the other CLBs to which it will be coupled. Thus, by storing different values in the memory cells, each CLB may be individually programmed as to its function and coupling.
The configuration data for the CLBs and the configurable routing matrices is stored in the configuration memory cells. The configuration data, once loaded into the configuration memory cells, selects the functions performed by the CLBs and connects the configurable routing matrices.
Recently, there has been a dramatic increase in the complexity and size of logic circuits used in a variety of applications. Since the number of CLBs that can be fabricated on a single integrated circuit chip is limited, this increasing number of circuit elements cannot be implemented with a single FPGA. Thus, there is a need to improve the efficiency with which CLBs implement logic functions.
One prior art approach to solve this shortcoming of existing FPGAs has been to connect multiple FPGAs externally. This approach, however, is only a partial solution. Due to the limited number of input/output connections between the FPGAs, not all circuits can be implemented by this approach. Moreover, using more than one FPGA increases the power consumption, cost, and space required to implement the circuit.
Another solution has been to increase the number of CLBs and interconnecting structures in the FPGA. For any given fabrication technology, there will be limitations to the number of CLBs that can be fabricated on an integrated circuit chip. Thus, there continues to be a need, from an architectural standpoint, to increase the logic gates or CLB densities for FPGAs.
While the prior art FPGAs may be re-configured to perform different logic functions at different times, it is necessary to reload a bit stream, which is time consuming. Re-configuration of an FPGA requires suspending the implementation of the logic functions, saving the current state of the logic functions in a memory device that is off the FPGA, re-loading the array of memory configuration cells, and inputting the states of the logic functions along with any other inputs. The re-loading of the configuration memory cells, itself, requires an amount of time that makes re-configuration not viable for implementing many circuits. It is more beneficial to increase the number of logic functions that are performed within an FPGA without sacrifices in speed and space.